OCP Unveils Specification for SoC Disaggregation Interface

Open Compute Project Foundation (OCP)

OCP Foundation (OCP), the nonprofit organization bringing hyperscale innovations to all, announced the release of the Bunch of Wires (BoW) specification for Chiplet interconnect.

The BoW specification represents a next step in the OCP Open Domain Specific Architecture (ODSA) Project’s march towards establishing an open Chiplet ecosystem as a catalyst for a new silicon market place and integrated circuit supply chain model.


BoW specifies a physical layer (PHY) optimized for System on a Chip (SoC) disaggregation, and complements OCP ODSA Open High Bandwidth Interconnect (OpenHBI) PHY specification targeting High Bandwidth Memory and other parallel bandwidth intensive use cases.

“The demand for specialized silicon has been increasing steadily due to workload diversity, such as with the adoption of AI and ML, and we expect this trend to continue for several years. In response to this demand the OCP recognizes that it must be a catalyst to establish open and standardized Chiplet ecosystems and new markets by investing in Chiplet interconnect technology that will enable composable silicon. The release of the BoW specification is an important step in this direction. We expect to increase our efforts on developing supply chain models for composable silicon,” said Bill Carter, CTO, OCP Foundation.

The ODSA BoW PHY specification is optimized for both commodity (organic laminate) and advanced packaging technologies, enabling cost and energy efficient, as well as high-performance designs across a wide range of process nodes. The specification was authored to allow many use cases driving significant economies of scale. Care was taken to impose as few constraints as possible and to avoid including required features in the specification that could increase design complexity when disaggregating an existing SoC.

The BoW specification, with an open license making it available to everyone, is already in use in at least 10 companies, including Samsung and NXP, over a dozen different use cases spanning 5, 6, 12, 16, 22 and 65nm process nodes, and covering Chiplet-based products for networking, specialized AI silicon, FPGAs, and processors.

“The semiconductor industry continues to innovate in new and exciting directions with multicore application specific SoCs, custom core architectures, deep learning, optical communications, analog processing techniques, RF interfaces, memory architectures and more. The new challenge is how to integrate all of these disparate innovations, several of which are not practical to produce at cutting- edge process nodes. Today’s announcement from the OCP ODSA, releasing the Bunch of Wires open-source specification for Chiplet interconnect, supplies a new tool toward expanding innovation in the market. This opens the door to a more competitive landscape and diversity in innovation at varying cadences and is fuel or a healthy industry,” said Tom Hackenberg, Principal Analyst, Computing & Software Semiconductor, Memory and Computing Division, Yole Intelligence.