New Options Create Single-instrument Solution that Eliminates Separate Clock Recovery Units for More Efficient, Highly Accurate Verification of High-speed Interconnects
Anritsu, a US based global provider of communications test and measurement solutions has introduced clock recovery options for its MP1800A Signal Quality Analyzer (SQA) that expand the analysis capability of the BERT in high-speed interconnect design applications. Integrating the clock recovery options into the MP1800A creates a single-instrument solution for signal integrity engineers to conduct highly accurate BER measurements and jitter tolerance tests on SERDES, Active Optical Cables (AOCs) and optical transceiver modules used in Next Generation Networks (NGNs) operating at speeds of 400 Gbit/s.
Traditionally, BER and jitter tolerance measurements of high-speed communications systems required external clock recovery instruments. The new internal clock recovery options in the MP1800A create a one-instrument test solution that reduces the cost of test, occupies less bench space, and improves accuracy. The new capability complements existing support of BERT and jitter measurements up to 32 Gbit/s, as well as highly accurate and ideal signal integrity analyses for various applications, including 100GbE (100G Base CR4, KR4), InfiniBand EDR, CEI-28G, and 32G Fibre Channel.
The MP1800A SQA is a modular-type BERT composed of an internal pulse pattern generator (PPG) and high-input-sensitivity error detector (ED) module, each of which can be configured with one, two, or four channels to support multi-channel synchronization of up to eight channels at 32 Gbit/s. A jitter modulation source can also be installed in the BERT to generate various types of jitter, including SJ, RJ, BUJ, and SSC, for device jitter tolerance tests. The plug-in modular design establishes an unprecedented level of customization to signal analysis of high-speed interconnects, allowing users to configure the MP1800A BERT to meet current test needs, with the flexibility to add measurement capability as needed.
Low jitter high-quality waveforms are achieved with the MP1800A because of the design of the BERT. The PPG has good output signal quality; tunable output amplitude over a wide range for adjusting signal output amplitude; and tunable data output phase. The ED has high input sensitivity of 10 mV. Up to 3.5 Vp-p output amplitude is achieved, enabling direct-drive EML.